Description
CPEG202 presents the design skills and theoretical knowledge needed to design, simulate, and build combinatorial logic circuits and basic sequential circuits. You are expected to attend lectures, study the modules, complete all exercises and projects, find additional relevant materials on the web, and use the CAD tools to extend your knowledge and experience beyond the assigned projects.
You are encouraged to complete lab project work outside of the Evans 134 lab at a time and place of your choosing, but you must come to Evans 134 during one of the posted sessions to have an assistant inspect and sign your work prior to submission. The lab is "open" and may be accessed at any time except when “closed” for other classes. Access requires a valid student ID card. You are welcome to use the lab at your convenience to complete the projects, and you may attend any or all sessions to get input from the assistants, fellow students, and/or the instructor.
You are encouraged to complete lab project work outside of the Evans 134 lab at a time and place of your choosing, but you must come to Evans 134 during one of the posted sessions to have an assistant inspect and sign your work prior to submission. The lab is "open" and may be accessed at any time except when “closed” for other classes. Access requires a valid student ID card. You are welcome to use the lab at your convenience to complete the projects, and you may attend any or all sessions to get input from the assistants, fellow students, and/or the instructor.
General Information
Textbook and Schedule
Our textbook has 10 modules and is published online at:
https://piazza.com/udel/spring2016/introductiontodigitalsystems/resources
You can also purchase the textbook in the bookstore.
Week 1. Feb 8. Module 1
Week 2. Feb 15. Module 1
Week 3. Feb 22. Module 2
Week 4. Feb 29. Module 3
Week 5. Mar 7. Module 4
Week 6. Mar 14. Module 5
Week 7. Mar 21. Exam 1
Week 8. Mar 28. SPRING BREAK
Week 9. Apr 4. Module 6
Week 10. Apr 11. Module 7
Week 11. Apr 18. Module 8
Week 12. Apr 25. Exam 2
Week 13. May 2. Module 9
Week 14. May 9. Module 10
May 17 (Tue) is the last day of classes and last lecture
May 19 (Thu) 7pm - 9pm Final Exam (SHL 130)
https://piazza.com/udel/spring2016/introductiontodigitalsystems/resources
You can also purchase the textbook in the bookstore.
Week 1. Feb 8. Module 1
Week 2. Feb 15. Module 1
Week 3. Feb 22. Module 2
Week 4. Feb 29. Module 3
Week 5. Mar 7. Module 4
Week 6. Mar 14. Module 5
Week 7. Mar 21. Exam 1
Week 8. Mar 28. SPRING BREAK
Week 9. Apr 4. Module 6
Week 10. Apr 11. Module 7
Week 11. Apr 18. Module 8
Week 12. Apr 25. Exam 2
Week 13. May 2. Module 9
Week 14. May 9. Module 10
May 17 (Tue) is the last day of classes and last lecture
May 19 (Thu) 7pm - 9pm Final Exam (SHL 130)
Grading
Combined exams scores will contribute 55% to your total point score(15% test 1, 15% test 2 and 25% final), and combined exercise and project scores will contribute 45%. Total combined scores will be normalized, and grades assigned on a percentage basis.
Late Policy
There is NO LATE Policy! Late assignments are not accepted. The course material and projects in CPEG202 builds on itself, so be careful not to fall behind. Catching up is extremely difficult, especially as other coursework picks up mid-semester.
Updated April 11, 2016: As discussed in lectures, late submission can be accepted if student works with Dean Shermyer to submit proof of extenuating circumstances and Dean's office sends the instructor an email regarding that absence being excused.
Updated April 11, 2016: As discussed in lectures, late submission can be accepted if student works with Dean Shermyer to submit proof of extenuating circumstances and Dean's office sends the instructor an email regarding that absence being excused.
Homework Policy
For homework exercises, you are encouraged to work with other students or knowledgeable individuals, but you must complete all submitted exercises yourself.
Project Policy
For projects, you are to work in groups of two. Projects are to be demonstrated to TA during weekly Friday lab session. Both partners must be present during the demo. Both partners must be able to complete the project on their own.
Project Grading Policy
Submitted projects must be inspected and signed-off by a lab assistant or no credit will be given. Partial credit is assigned by the in-lab TAs. The in-lab TA's will inspect your work, and ask you a series of relevant questions about your submissions. These questions allow the TA to better assess your work, to ensure that you understand completely all that you are submitting, and to verify that the work is your own. Duplicate submissions will receive no points. Grading questions or grievances may be brought to the course instructor for resolution.
Class Hardware
The Basys2 circuit boards are used for weekly class projects. These boards can be purchased from UDEL Bookstore after February 9th. Alternatively, the same board can be purchased from DIGILENT from here: http://store.digilentinc.com/basys-2-spartan-3e-fpga-trainer-board-limited-time-see-basys-3/
Class Software
The Xilinx CAD software will be used to design circuits that can be programmed into your circuit board. The Xilinx ISE software is full-featured and designed for practicing engineers. Instructions for loading this software are at: https://piazza.com/class/ijyr63w52lg7n2?cid=6
Video Recording of Lectures
Recorded class lectures can be viewed @ http://udcapture.udel.edu/2016s/cpeg202-010/
Lecture Location and Time
Lectures are given Tuesday and Thursday 3:30pm - 4:45pm in SHL130
Extra Credit
From time to time, we will announce extra credit assignments which will allow you to earn extra points in the class. Example is: https://piazza.com/class/hr8efct4cfn7g9?cid=16
Project Demos (FRI 9-12pm, 3:30pm-7:30pm)
Lab demonstrations are done over 10 minute meeting with TAs on Fridays. We have two blocks of time on Friday to sign-up. Please upload your bit files to SAKAI prior your demo. Demo signup is done on Piazza.
When are things due on SAKAI
Projects are due on SAKAI on Fridays' before 9AM
Homeworks are due on SAKAI on Fridays' before 11:55PM
Homeworks are due on SAKAI on Fridays' before 11:55PM
Policy on Breaking-up (Added 4/20/16)
In CPEG202, we permit “no fault” break-up of partnerships. We also allow new partnerships to form. If you break up or form a new a partnership - please let the professor know via email. We will only accommodate changes until empty slots are full (we have 10 right now). The partner/s initiating the change must arrange to demo at one of the free times unless the other partner wants a different time. Each student can only change partners once.
Name | Office Hours | |
---|---|---|
Fouad Kiamilev | When? Where? | |
Rebekah Houser | When? Where? | |
Hamza Lemsaddek | When? Where? | |
Ben Mazur | When? Where? | |
Johnny Rutkowski | When? Where? | |
Olga Mironenko | When? Where? | |
Furkan | When? Where? |