Description

This course has been designed to teach the fundamental techniques for designing and implementing digital logic systems by understanding formal foundations and selected techniques. During this course, designing of digital circuit will be developed in the students more as an art than a science. This art will further be groomed with practical implementation on current available digital circuit families.

Student Learning Outcomes:
The specific course outcomes supporting the program outcomes are:
1. Students should be able to solve basic binary math operations using the logic gates.
2. Students should be able to demonstrate programming proficiency using the various logical elements to design practically motivated logical units.
3. Students should be able to design different units that are elements of typical computer’s CPU.
4. Students should be able to apply knowledge of the logic design course to solve problems of designing of control units of different input/output devices.
5. Students should be able to wiring different logical elements, to analyze and demonstrate timing diagrams of the units modeled.
6. Students should be able to design electrical circuitry using logical elements realized on the base of different technologies.

General Information

Instructor's Contact Information:
muhammad.umer@cs.uol.edu.pk

Announcements

DLD Mid Term Exam
1/03/17 4:36 PM

DLD Mid Term Exam Paper:

DLD_Mid_Term_Exam.pdf

Solution:

DLD_Mid_Term_Solution.pdf

Course Survey
12/14/16 3:27 PM

Please, fill this course survey feedback form using following link:

https://goo.gl/uoVHzj

Deadline: December 21, 2016

 

Xilinx_ISE_Tutorial.pdf has been added to class homepage under Resources
11/29/16 2:23 PM

The teaching staff has posted a new general resource.

Title: Xilinx_ISE_Tutorial.pdf
http://www.piazza.com/class_profile/get_resource/iuz3knuu3th436/iw3amddz7k23v7


You can view it on the course page: https://piazza.com/uol.edu.pk/fall2016/cs4349/resources

Project Choices and Guidelines
11/25/16 3:38 PM

Notes:
1. See course outline for weight-age.
2. Students can take any choice but the Choice A is recommended.
3. Project can be done in a group of maximum four people (not in every case), but grading will be done separately on the basis of individuals’ contribution.

Choice A: ‘Digital Design’ by Engineering a Real Life Problem


What: Students have to engineer a real life problem to provide a complete Digital Design.
How: You are guided to pick a problem, you or people around you, are facing, and then engineer it. The yield of this engineering may be an implemented circuit, a design described & simulated in HDL, a burnt code chip of the available kits. Groups will display their work on the said date and submit the project report as per schedule.
For Example: You can try any of the following or alike things.
• Implement a design on breadboard or on available laboratory equipment, using discrete components or ICs available in the market. Take a lab & market survey, before you start, as this is how you would know the best available resources.
• Describe a design in HDL, Verilog preferably, and simulate your design flawlessly. Once you have achieved that you can also burn that code on any of the available FPGA Kits.

When: Display would be on January 01, 2016 and on wards.

Choice B: ‘Seminar’ on Advanced Topics

What: Students have to give a seminar on the chosen or assigned topic.
How: The seminar must be well researched & organized and should convey the concept and knowledge; it’s not an ordinary presentation. It can range from 30 to 60 minutes. Entire class must be involved and on-board. It must
reflect the Book Study and Literature Review.
For Example: You can do it in the either way.
• Search for the advanced topics in Digital Design or better to refer the primary text book.
• Study a research work by choosing a paper from reputed journals or highly ranked digital libraries like IEEE Xplore, understand it and present.
• Topic may be anything like any design technique, associated engineering areas and digital design, or any other autonomous topic.
When: on assigned date.

Instructions:
1. All the seminar topics need an approval and date that can be taken from the instructor on verbal discussion.
2. All the students must notify before starting any work, or in case of any change in the project topic, in order to avoid the repetition.


Y O U R    T I M E    S T A R T S   N O W…

KMap_Simulator.ppt has been added to class homepage under Resources
11/25/16 3:15 PM

The teaching staff has posted a new undefined resource.

Title: KMap_Simulator.ppt


You can view it on the course page: https://piazza.com/uol.edu.pk/fall2016/cs4349/resources

Staff Office Hours
NameOffice Hours
Rao Muhammad Umer
When?
Where?