Description
General Information
Email : vkarna@eng.ucsd.edu
Office hours: Wednesday’s 6:20-7:00pm (Zoom). Also students can request for zoom session on any other day post 5 PM my sending me an e-mail in advance
Lectures will be conducted on zoom platform each week on :
M, W 5:00-6:20 PM
Note : Visit canvas course webpage to find zoom video conference links for each lecture. See Canvas webpage link below.
https://canvas.ucsd.edu/courses/33921/external_tools/628
Zoom Meeting Password : galileo111
TA : Brandon Saldanha (email : bsaldanha@ucsd.edu)
TA : Naman Sehgal (email : nsehgal@ucsd.edu)
TA : Vijayalakshmi Swaminathan (email : vswaminathan@ucsd.edu)
Tutor : Shengfan Hu (email : shh042@ucsd.edu)
For TA and Tutor zoom interactive session hours refer to :
https://piazza.com/ucsd/winter2022/ece111/staff
Note : On canvas zoom meeting links for each week course sessions are published under "Syllabus"
- Learn how to design combinational and sequential circuits using SystemVerilog language
- Synthesis each design example and visualize logic circuit which will be implemented inside FPGA
- Learn how to develop SystemVerilog directed tests, perform RTL simulation and debug waveforms
- Learn SystemVerilog design modeling styles and how to develop FSM's
- SystemVerilog Synthesis Coding Guidelines through example
- Digital design timing and pipeling fundamentals
- Understand FPGA architecture and synthesis flow
- Understand FPGA and ASIC frontend and backend design flow differences
- Learn how to use EDA tools such as Altera Quartus prime and Modelsim to implement and simulate hardware logic specified in SystemVerilog
- Event driven vs Cycle accurate simulation concept
- Develop synthesizable SHA256 cryptograhic hashing module and bitcoin hasing model in final project
- Through weekly homework assignments develop simpler to complex synthesizable hardware models
-There will be one quiz in Mid to Late Feb 2022 timeframe. Date will be announced before time for students to prepare.
- Quizz outline will be provided to students
Assignments : 45% of final grade
-There will be multiple programming-based assignments. Which will include designing circuits using SystemVerilog, develop testbench, perform synthesis and simulation.
-One of the assignment would be open-ended and student to decide what they would like to design, synthesis and simulate
-For details on assignments and deadlines will be published on the schedule page.
Final project and presentation : 35% of final grade
-RTL code development, FPGA synthesis, Verification and Final Presentation
-More information on the final project will be presented later in this quarter.
Author : Stuart Sutherland
ISBN-13: 978-1546776345
ISBN-10: 1546776346
- Digital Design and Computer Architecture: ARM Edition 1st Edition
Author : Sarah Harris and David Money Harris
ISBN-13: 978-0128000564
ISBN-10: 9780128000564
-SystemVerilog LRM (Language Reference Manual)
https://standards.ieee.org/standard/1800-2012.html
-Accellera Home Page :
https://www.accellera.org/downloads/standards
Announcements
I Will be submitting grades tomorrow afternoon so upload any missing HW's or Final Project by noon tomorrow
Regards,
Vishal Karna
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Dear Students,
Many of you have sent me email regarding great support from ECE-111 Teaching Assistants and Tutor's. Lets applaud their efforts and join me to thank each TA and Tutor.
Thank you Viji, Brandon, Zixiang, Shengfan and Naman for your continuous support on homework assignments, lecture material understanding and especially your support on Final Project is highly appreciated. Good Job !
Regards,
Vishal Karna
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Hi everyone
I will be available from 11:15 - 1:15 tomorrow to clear last minute doubts if any.
Dear Students,
Looks like some of you are still working on Final Project. I will extend the deadline to tomorrow 5 PM PST.
Please do not delay beyond that. So you have some more time to complete.
Regards,
Vishal Karna
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Hi everyone,
If you need help with your project, please email me so that we can schedule one on one office hours.
Here’s my email address: ziz358@ucsd.edu
Hi Everyone
I will provide extra office hour from 5:00 pm to 6:30 pm today. If there are too many students join in my office hour please wait patiently, I will extend my office hour like yesterday.
Best
Shengfan
Hi All,
If You have uploaded .rar files for your final project, then you need to upload .zip folder which works on windows. I will not able to access .rar and this will result in no grades. So make this correction and upload ASAP today and let me know.
Thanks
Vishal Karna
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Hi everybody,
I will be having extra OH from 12:00 noon to 5:00 PM today.
Update: I will be back after an hour's break.
| Name | Office Hours | |
|---|---|---|
Zhou Zixiang | When? Where? | |
Vishal Karna | When? Where? | |
Vijayalakshmi Swaminathan | When? Where? | |
Brandon Saldanha | When? Where? | |
Naman Sehgal | When? Where? | |
Yatish Turakhia | When? Where? |